109 questions in 4 topics. Try each one before you press "Show answer".
Consider the real valued variables X, Y and Z represented using the IEEE -754 single precision floating-point format. The binary representations of X and Y in hexadecimal notation are as follows: X: 35C00000 Y: 34A00000 Let Z = X + Y. Which one of the following is the binary representation of Z, in hexadecimal notation?
Consider the 8-bit signed integers X, Y and Z represented using the sign-magnitude form. The binary representations of X and Y are as follows: X: 10110100 Y: 01001100 Which of the following operations to compute Z result(s) in an arithmetic overflow?
In a system, numbers are represented using 4- bit two's complement form. Consider four numbers N1 = 1011, N2 = 1101, N3 = 1010 and N4 = 1001 in the system. Which of the following operations will result in arithmetic overflow?
The 32-bit IEEE 754 single precision representation of a number is 0XC2710000. The number in decimal representation is ________ (rounded off to two decimal places).
The number 6 can be represented as 1010 in 4- bit 2's complement representation. Which of the following is/are CORRECT 2's complement representation(s) of -6?
The following two signed 2's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm: M: 1100110111101101 Q: 1010010010101010 The total number of addition and subtraction operations to be performed is __________. DIGITAL LOGIC
Which of the following is/are EQUAL to 224 in radix-5 (i.e., base-5) notation?
Consider a system that uses 5 bits for representing signed integers in 2's complement format. In this system, two integers A and B are represented as A = 01010 and B = 11010. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow?
A particular number is written as 132 in radix-4 representation. The same number in radix-5 representation is __________.
Consider three floating point numbers A, B and C stored in registers RA, RB and RC, respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows. RA = 0xC1400000 RB = 0x42100000 RC = 0x41400000 Which one of the following is FALSE?
Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which one of the following values of R1 and R2 gives an arithmetic overflow?
If the numerical value of a 2-byte unsigned integer on a little-endian computer is 255 more than that on a big-endian computer, which of the following choices represent(s) the unsigned integer on a little-endian computer?
If x and y are two decimal digits and (0.1101)2=(0.8xy5)10, the decimal value of x+y is?
Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?
Consider Z = X - Y where X, Y and Z are all in sign- magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of: DIGITAL LOGIC
In 16-bit 2's complement representation, the decimal number 28 is:
Two numbers are chosen independently and
uniformly at random from the set {1, 2, ..., 13}. The
probability (rounded off to 3 decimal places) that
their 4-bit (unsigned) binary representations have
the same most significant bit is ______.Consider the unsigned 8-bit fixed point binary Number System below: b7b6b5b4b3b2b1b0 where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit (MSB). Some of the decimal numbers listed below cannot be represented exactly in the above representation: (i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001 Which one of the following statements is true?
The representation of the value of a 16-bit unsigned integer X in the hexadecimal number system is BCA9. The representation of the value of X in octal number system is
Let X be the number of distinct 16-bit integers in 2's complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X - Y is _____
The 16-bit 2's complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________.
Consider the equation (43)x = (y3)8 where x and y are unknown. The number of possible solutions is ________
Consider the equation (123)5 = (x8)y with x and y as unknown. The number of possible solutions is ______.
The base (or radix) of the number system such that the following equation holds 312 20 = 13.1 is ____________ DIGITAL LOGIC
The smallest integer that can be represented by an 8-bit number in 2's complement form is
P is a 16-bit signed integer. The 2's complement representation of P is (F87B)16. The 2's complement representation of 8 × P is
(1217)8 is equivalent to
The two numbers given below are multiplied using the Booth's algorithm. Multiplicand: 0101 1010 1110 1110 Multiplier: 0111 0111 1011 1101 How many additions/Subtractions are required for the multiplication of the above two numbers?
Let r denote the number system radix. The only value(s) of r that satisfy the equation √121r = 11r is/are
Consider numbers represented in 4-bit Gray code. Let h3 h2 h1 h0 be the Gray code representation of a number n and let g3 g2 g1 g0 be the Gray code of (n + 1) (modulo 16) value of the number. Which one of the following functions is correct?
We consider the addition of two 2's complement numbers bn-1 bn-2 ... b0 and an-1 an-2 ... a0. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by cn-1 cn-2 ... c0 and the carry-out by cout. Which one of the following options correctly identifies the overflow condition?
When multiplicand Y is multiplied by multiplier X = xn-1 xn-2 ... x0 using bit-pair recoding in Booth's algorithm, partial products are generated according to the following table. DIGITAL LOGIC The partial products for rows 5 and 8 are?
Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as
The range of integers that can be represented by an n-bit 2's complement number system is:
The hexadecimal representation of (657)8 is:
Consider the Boolean expression F(P, Q) = (P̅ + Q) ⊕(P̅Q). Which of the following expressions is equivalent to F?
Consider a Boolean function F with the following min-term expression: F(P, Q, R, S) = Σm(1, 2, 3, 4, 5, 7, 10, 12, 13, 14) Which of the following options is/are the minimal sum-of-products expression(s) of F?
Consider the following 4-variable Boolean function F(A, B, C, D) = Σm(0, 1, 2, 3, 8, 9, 10, 11) Consider A as MSB, D as LSB. Which one of the following options represents the minimal sum of products form for the above function? Note: + is OR operation, · is AND operation, ' is NOT operation
Which one of the following options is not a property of Boolean Algebra?
Which of the following Boolean algebraic equation(s) is/are CORRECT?
Let X be a 3-variable Boolean function that produces output as '1' when at least two of the input variables are '1'. Which of the following statement(s) is/are CORRECT, where a, b, c, d, e are Boolean variables?
For a Boolean variable x, which of the following statements is/are FALSE?
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?
Consider the following Boolean expression. F = (X + Y + Z)(X̅ + Y)(Y̅ + Z) Which of the following Boolean expressions is/are equivalent to F̅ (complement of F)?
Which one of the following is NOT a valid identity?
Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?
If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?
Let, x1 ⊕ x2 ⊕ x3 ⊕ x4 = 0 where x1, x2, x3, x4 are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE?
Consider the Boolean operator # with the following
properties:
x # 0 = x
x # 1 = x̅
x # x = 0
x # x̅ = 1
Then x # y is equivalent toThe number of min-terms after minimizing the following Boolean expression is ________. [D' + AB' + A'C + AC'D + A'C'D]'.
The dual of a Boolean function F(x1, x2, . . ., xn) written as FD is the same expression as that of F with + and · swapped. F is said to be self-dual if F = FD. The number of self-dual functions with n Boolean variables is
Let ⊕ denote the exclusive OR (XOR) operation. Let '1' and '0' denote the binary constants. Consider the following Boolean expression for F over two variables P and Q: F(P, Q) = ((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0)) The equivalent expression for F is
Which one of the following expressions does NOT represent exclusive NOR of x and y?
The truth table represents the Boolean function
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?
What is the boolean expression for the output of the combinational logic circuit of NOR gates given below?
What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates?
If P, Q, R are Boolean variables, then (P + Q̅)(P·Q̅ + P·R)(P̅·R + Q̅) simplifies to
Given f1,f2 and f in the canonical sum of products form(in decimal) for the circuit f1 = Σm(4, 5, 6, 7, 8) f3 = Σm(1, 6, 15) f = Σm(1, 6, 8, 15) then f2 is
Define the connective * for the Boolean variables X
and Y as:
X * Y = XY + X'Y'.
Let Z = X * Y. Consider the following expressions
P, Q and R.
P: X = Y * Z,
Q: Y = X * Z,
R: X * Y * Z = 1
Which of the following is TRUE?Let f(w,x,y,z) = Σ (0,4,5,7,8,9,13,15). Which of the
following expressions are NOT equivalent to f?
P: x'y'z' + w'xy' + wy'z + xz
Q: w'y'z' + wx'y' + xz
R: w'y'z' + wx'y' + xyz + xy'z
DIGITAL LOGIC
S: x'y'z' + wx'y' + w'yThe following expression was to be realized using 2-input AND and OR gates. However, during the fabrication all 2-input AND gates were mistakenly substituted by 2-input NAND gates. (a.b).c + (a'.c).d + (b.c).d + a.d . What is the function finally realized?
The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map. Which of the product terms given below is an essential prime implicant of the function?
Which of the following expressions is equivalent to (A ⊕ B) ⊕ C ?
Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent an active-high 2:4 decoder and a 4-to-1 multiplexer, respectively. Out of 16 possible input combinations, the number of combinations that produce Y = 1 is __________. (Answer in integer).
Consider the following logic circuit diagram. Which is/are the CORRECT option(s) for the output function F?
A Boolean digital circuit is composed using two 4- input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0-X7 are the inputs of the multiplexers M1 and M2 and could be connected to either 0 or 1. The select lines of the multiplexers are connected to Boolean variables A, B and C as shown. Which one of the following set of values of (X0, X1, X2, X3, X4, X5, X6, X7) will realise the Boolean function A'+ A'⋅C' + A⋅ B'⋅C?
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16- bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T? DIGITAL LOGIC
Which one of the following circuits implements the Boolean function given below? f (x, y, z) = m0 + m1 + m3 + m4 + m5 + m6, where mi is the ith min- term.
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2's complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is ______.
Consider a carry look ahead adder for adding two n- bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is:
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.
Consider the 4-to-1 multiplexer with two select lines S1 and S0 given below The minimal sum of products form of the output X is
Consider the following combinational function
block involving four Boolean variables x, y, a, b
where x, a, b are inputs and y is the output.
f(x,y,a,b)
{
if(x is 1)y =a;
else y=b;
}
Which one of the following digital logic blocks is
the most suitable for implementing this function?In the following truth table, V = 1 if and only if the input is valid. In the following truth table, V = 1 if and only if the input is valid. Inputs D0 D1 D2 D3 0 0 0 0 1 0 0 0 x 1 0 0 x x 1 0 x x x 1 Output X0 X1 V x x 0 0 0 1 0 1 1 1 0 1 1 1 1 What function does the truth table represent?
The amount of ROM needed to implement a 4 bit multiplier is?
The Boolean expression of the output of the multiplexer shown below is
Which one of the following adders reduces carry propagation delay by generating carries in advance?
The line in the following figure is permanently connected to the ground. Which of the following inputs (X1 X2 X3 X4) will detect the fault?
In a look-ahead carry generator, the carry generates function Gi and the carry propagate function Pi for inputs Ai and Bi are given by: Pi = Ai ⊕ Bi and Gi = AiBi The expressions for the sum bit Si and the carry bit Ci+1 of the look ahead carry adder are given by: Si = Pi ⊕ Ci and Ci+1 = Gi + PiCi, where C0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:
Consider the circuit below. Which one of the following options correctly represents f(x,y,z)
The majority function is a Boolean function f(x,y,z)that takes the value 1 whenever a majority of the variables x, y, z are 1. In the circuit diagram for DIGITAL LOGIC the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively.
Given two three-bit numbers a2 a1 a0 and b2 b1 b0 and c the carry in, the function that represents the carry generate function when these two numbers are added is:
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops. Input Current State Next State P Q1 Q1 + Q0 + 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0
Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go through before returning to the initial state is . (Answer in integer)
In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is ________. (Answer in integer)
The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options
Consider a digital logic circuit consisting of three 2- to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are DIGITAL LOGIC inputs of M2. A, B, and C are select lines of M1, M2, and M3, respectively. For an instance of inputs X1= 1, X2= 1, X3= 0, and X4= 0, the number of combinations of A, B, C that give the output Y= 1 is ____________.
Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q3 have values 0, 1 and 1, respectively. Which one of the given values of (Q1, Q2, Q3) can NEVER be obtained with this digital circuit?
Consider a 3-bit counter, designed using T flip-flops, as shown below : Assuming the initial state of the counter given by PQR as 000, what are the next three states?
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
The next state table of a 2-bit saturating up-counter is given below. Q1 Q0 Q1 + Q0 + 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 DIGITAL LOGIC The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is __________.
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip- flops have non-zero propagation delays.
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a ?
The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycles is
The minimum number of D flip-flops needed to design a mod-258 counter is
Consider the following circuit involving three D- type flip-flops used in a certain type of counter configuration If at some instance prior to the occurrence of the clock edge, and have a value , and respectively, what shall be the value of after the clock edge?
In the sequential circuit shown below, if the initial value of the output is . What are the next four values of ?
What is the final value stored in the linear feedback shift register if the input is 1011101?
The control signal functions of a - binary counter are given below (where is "don't care"): DIGITAL LOGIC Assume that the counter and gate delays are negligible. If the counter starts at then it cycles through the following sequence
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?
Consider the circuit in the diagram. The operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared) The following data: is supplied to the "data" terminal in nine clock cycles. After that the values of q2q1qo are:
Consider the following circuit The flip-flops are positive edge triggered s. Each state is designated as a two-bit string . Let the initial state be The state transition sequence is
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let represents the logic level on the line in the -th clock period Let represent the complement of . The correct output sequence on over the clock periods through is: