Hardwired control unit

Why it exists

The datapath tells us which control signals each step needs. Something has to produce them, step after step, in response to the instruction in IR. In a hardwired control unit that something is a combinational logic circuit plus a counter: no memory of microinstructions, just gates. Each control signal is a Boolean function of which step we are in, which instruction it is and the condition flags. Because it is pure logic, it is the fastest way to generate the signals, and it is what simple, fast (RISC-style) processors use. Its cost is that the logic is irregular and grows with the number of instructions, so changing or extending the instruction set means redesigning gates. GATE asks for the equation of a signal, which signals are active in a given step, the structure of the unit, and the comparison with the microprogrammed unit.

Prerequisites

You need the control sequences of the datapath and the design of sequential circuits from state machines.

Precise definitions

Structure of a hardwired control unit.

• A control step counter (or one-hot ring counter) that counts the control steps $T_1, T_2, \dots$ of the current instruction and is cleared by the End signal.
• A step decoder that converts the counter value into one active line per step ($T_i$ = 1 only in step $i$).
• An instruction decoder that converts the opcode in IR into one active line per instruction (ADD, LOAD, ...), a decoder.
• The control signal logic: for every control signal an OR of AND terms of step lines and instruction lines (and flags).
• Inputs: IR, the counter, the condition code flags, external signals such as the memory's "function completed" and interrupt requests.

Equation of a control signal. Read off from the table of sequences: the signal is active in a step, for all instructions or for a particular one. For the two-instruction machine of the datapath page:

The signals that are the same in every instruction depend only on the step ($T_1$ to $T_3$ form the fetch); those that depend on the instruction are ANDed with its decoder line. A branch instruction would add a term with a flag, for example $\text{PCin} = T_2 + T_k \cdot \text{BRANCH} \cdot \text{Z}$.

As a state machine. The control unit is a Moore machine: its state is (step, instruction), its outputs are the control signals, and the inputs are IR, the flags and memory completion; the step counter plus decoder is one way to implement the state register. If the longest instruction needs $k$ steps the counter needs $\lceil \log_2 k \rceil$ flip-flops (or $k$ in a one-hot ring).

Implementation styles. Direct logic (as above), a PLA for the OR-of-ANDs, or the delay-element method, where a chain of delay elements replaces the counter and each control step is the output of the next element.

Properties. Fast (the delay is a few gate levels, so it hardly slows the clock). Compact for small, regular instruction sets. Hard to design for large, complex instruction sets (many terms, irregular), hard to change (a change means rewiring logic), and hard to debug. This is why RISC processors with few, regular instructions use it, while complex instruction sets are usually microprogrammed (microprogrammed control).

How it works

The timing diagram shows the signals while ADD R1,R2 runs. The step counter (a bus) advances from $T_1$ to $T_6$; at each step exactly the signals of that row of the table are 1. The first three steps are the same for every instruction; from $T_4$ on the signals depend on the instruction decoded from IR (ADD here).

The same machine for LOAD R3,(R2) asserts different signals in $T_4$ to $T_6$ but the same ones in $T_1$ to $T_3$; this is why the step counter is shared, and only the instruction decoder lines change the outputs.

Worked examples

#include <stdio.h>
 
enum { PCout, PCin, MARin, MDRout, IRin, Yin, Zin, Zout, R1out, R1in, R2out, R3in, Read, WMFC, Select4, SelectY, Add, End, NSIG };
static const char *name[NSIG] = { "PCout", "PCin", "MARin", "MDRout", "IRin", "Yin", "Zin", "Zout", "R1out", "R1in", "R2out", "R3in", "Read", "WMFC", "Select4", "SelectY", "Add", "End" };
#define B(x) (1 << (x))
 
/* the table of control steps: steps 1 to 3 are the fetch, 4 to 6 belong to the instruction */
static const int table[2][6] = {
    { B(PCout) | B(MARin) | B(Read) | B(Select4) | B(Add) | B(Zin), B(Zout) | B(PCin) | B(Yin) | B(WMFC), B(MDRout) | B(IRin),
      B(R1out) | B(Yin), B(R2out) | B(SelectY) | B(Add) | B(Zin), B(Zout) | B(R1in) | B(End) },
    { B(PCout) | B(MARin) | B(Read) | B(Select4) | B(Add) | B(Zin), B(Zout) | B(PCin) | B(Yin) | B(WMFC), B(MDRout) | B(IRin),
      B(R2out) | B(MARin) | B(Read), B(WMFC), B(MDRout) | B(R3in) | B(End) },
};
 
/* the hardwired control unit: each signal is an OR of terms (control step) AND (instruction decoder output) */
static int hardwired(int sig, int t, int add, int load) {
    int T1 = t == 1, T2 = t == 2, T3 = t == 3, T4 = t == 4, T5 = t == 5, T6 = t == 6;
    switch (sig) {
    case PCout: return T1;
    case PCin: return T2;
    case MARin: return T1 || (T4 && load);
    case MDRout: return T3 || (T6 && load);
    case IRin: return T3;
    case Yin: return T2 || (T4 && add);
    case Zin: return T1 || (T5 && add);
    case Zout: return T2 || (T6 && add);
    case R1out: return T4 && add;
    case R1in: return T6 && add;
    case R2out: return (T5 && add) || (T4 && load);
    case R3in: return T6 && load;
    case Read: return T1 || (T4 && load);
    case WMFC: return T2 || (T5 && load);
    case Select4: return T1;
    case SelectY: return T5 && add;
    case Add: return T1 || (T5 && add);
    default: return T6 && (add || load);      /* End */
    }
}
 
int main(void) {
    int bad = 0, total = 0;
    for (int ins = 0; ins < 2; ins++)
        for (int t = 1; t <= 6; t++)
            for (int s = 0; s < NSIG; s++) {
                int want = (table[ins][t - 1] >> s) & 1;
                int got = hardwired(s, t, ins == 0, ins == 1);
                bad += want != got;
                total++;
            }
    printf("hardwired equations differ from the control-step table in %d of %d cases\n", bad, total);
    printf("ADD, step T5 asserts:");
    for (int s = 0; s < NSIG; s++)
        if (hardwired(s, 5, 1, 0)) printf(" %s", name[s]);
    printf("\nLOAD, step T5 asserts:");
    for (int s = 0; s < NSIG; s++)
        if (hardwired(s, 5, 0, 1)) printf(" %s", name[s]);
    printf("\n");
    int uses = 0;
    for (int s = 0; s < NSIG; s++) {
        int terms = 0;
        for (int ins = 0; ins < 2; ins++)
            for (int t = 1; t <= 6; t++) terms += ((table[ins][t - 1] >> s) & 1);
        uses += terms > 0;
    }
    printf("%d signals, each driven by an OR of (T step) AND (instruction) terms\n", uses);
    return 0;
}

hardwired equations differ from the control-step table in 0 of 216 cases
ADD, step T5 asserts: Zin R2out SelectY Add
LOAD, step T5 asserts: WMFC
18 signals, each driven by an OR of (T step) AND (instruction) terms

Cheat box

Traps and GATE patterns

Connections

The table the equations come from is the datapath's control-step table. The instruction decoder is a decoder and the step counter is a counter. The alternative of storing the control words in a memory is microprogrammed control. Hardwired control is one reason RISC designs (RISC versus CISC) can reach high clock speeds.

PYQs

A hardwired CPU uses 10 control
signals S1 to S10, in various time steps T1 to T5, to
implement 4 instructions I1 to I4 as shown below:

T1
T2
T3
T4
T5
I1
S1, S3, S5
S2, S4, S6
S1, S7
S10
S3, S8
I2
S1, S3, S5
S8, S9, S10
S5, S6S7
S6
S10
I3
S1, S3, S5
S7, S8, S10
S2, S6, S9
S10
S1, S3
I4
S1, S3, S5
S2, S6, S7
S5, S10
S6, S9
S10

Which of the following pairs of expressions
represent the circuit for generating control
signals S5 and S10 respectively?
((Ij + Ik)Tn indicates that the control signal
should be generated in time step Tn if the
instruction being executed is Ij or lk)
S10 = (I1 + I3) ⋅ T4 + (I2 + I4) ⋅ T5
(b)
S5 = T1 + (I2 + I4) ⋅ T3 and
S10 = (I1 + I3) ⋅ T4 + (I2 + I4) ⋅ T5
(c)
S5 = T1 + (I2 + I4) ⋅ T3 and
S10 = (I2 + I3 + I4) ⋅ T2 + (I1 + I3) ⋅ T4
+(I2 + I4) ⋅ T5
(d)
S5 = T1 + (I2 + I4) ⋅ T3 and
S10 =(I2 +I3). T2 +I4.T3 +(I1+I3).

S10 = (I2 + I3) ⋅ T2 + I4 ⋅ T3 + (I1

+I3 ) ⋅ T4 + (I2 + I4) ⋅ T5

Self-check

Revision card

References