Synchronous and asynchronous counters

Why it exists

A counter is a register that steps through a fixed sequence of states, one step per clock pulse. It counts events, divides a clock frequency, generates addresses (the program counter), makes timing signals and steps a control unit. There are two ways to build one. The asynchronous (ripple) counter is the cheapest: the output of each flip-flop clocks the next, so the clock ripples down the chain. The synchronous counter clocks every flip-flop together and uses gates to decide which flip-flops toggle. GATE asks for the count sequence, the modulus, the frequency of an output, the maximum clock frequency, the glitches of a ripple counter, the number of flip-flops, and the input equations of a synchronous design.

Prerequisites

You need T and JK flip-flops and the excitation table from flip-flop conversion.

Precise definitions

Modulus. An $n$-bit counter that uses all its states has modulus $2^n$ (a mod-$2^n$ counter): 3 bits count 0 to 7, 4 bits 0 to 15. A mod-$N$ counter has $N$ states and needs $\lceil \log_2 N \rceil$ flip-flops. The decade (BCD) counter is mod-10 with 4 flip-flops.

Frequency division. Each flip-flop of a binary counter divides the frequency by 2. If the clock has frequency $f$, the output $Q_i$ (counting from $Q_0$) has frequency $f / 2^{i+1}$. A mod-$N$ counter's last stage divides by $N$ when it produces one output pulse per cycle.

Asynchronous (ripple) counter. T flip-flops with $T = 1$ (or JK with $J = K = 1$). The first is clocked by the external clock, and each following flip-flop is clocked by the output of the previous one.

For a falling-edge flip-flop clocked by $Q_i$: when $Q_i$ falls from 1 to 0 (the stage wraps from 1 back to 0) the next stage toggles, which is exactly the carry of a binary counter.

Ripple delay and glitches. Each stage changes only after the previous one, so a change at the input ripples through the chain with a delay $t_{pd}$ per stage. After a clock edge the counter passes through intermediate false counts: the worst case, 011 to 100, shows 011, then 010, then 000, then 100. The outputs are valid only $n \cdot t_{pd}$ after the clock edge, so the clock period must exceed $n\,t_{pd}$ and the maximum clock frequency is about $1 / (n\,t_{pd})$: it falls as the counter gets longer. A decoder on the outputs can respond to the false counts.

Mod-$N$ ripple counter by reset. For a count of $N$ states, add a gate that detects the state $N$ and clears all flip-flops asynchronously. The counter then counts $0, \dots, N-1$, but the state $N$ exists for a very short time (a glitch) before the clear takes effect.

Synchronous counter. All flip-flops share the clock, so all changes happen at the same time. For a binary up counter with T flip-flops:

$T_0 = 1,\quad T_1 = Q_0,\quad T_2 = Q_1 Q_0,\quad T_i = Q_{i-1}\cdots Q_1 Q_0 ,$

that is, a stage toggles when all lower bits are 1. For a down counter each $Q$ in the AND is complemented ($T_i = Q_{i-1}' \cdots Q_0'$). An up-down counter selects between them with a control input. Delay: one flip-flop delay plus the delay of the largest AND gate, independent of the number of stages in the simple model, so a synchronous counter can run faster than a ripple counter of the same size and has no false counts.

Design procedure for a synchronous counter with any sequence. (1) Draw the state sequence and assign the flip-flop outputs. (2) For each present state find the next state. (3) From the excitation table of the chosen flip-flop type, find the required inputs for every flip-flop. (4) Treat unused states as don't cares and minimise each input equation with a K-map. (5) Check what the unused states do: the design should lead them back into the main sequence (self-correcting).

Ring counter. An $n$-stage shift register whose last output feeds the first input; initialised to one-hot (1000...). It cycles through $n$ states, one flip-flop per state, and its outputs are directly the timing signals. Johnson (twisted-ring) counter. The same but with the inverted last output fed back: $n$ flip-flops give $2n$ states. A 3-stage Johnson counter runs 000, 100, 110, 111, 011, 001. Each state can be decoded with a 2-input AND gate. Both have unused states ($2^n - n$ and $2^n - 2n$) and need a self-starting circuit or an initial reset.

How it works

Step through a 3-bit asynchronous counter. Falling clock edges are marked by the cursor. Watch the bus line at the bottom around the transition from 3 to 4: the three bits do not change together, so the count passes through 010 and 000 on the way from 011 to 100.

Now the same counter with all flip-flops on one clock and $T_0 = 1$, $T_1 = Q_0$, $T_2 = Q_1Q_0$. All changes line up and the count goes straight from 011 to 100.

For a design example, a synchronous mod-6 counter (states 0 to 5) with T flip-flops. The top bit toggles on the transitions 3 to 4 and 5 to 0, so $T_2$ is 1 in states 3 and 5; the unused states 6 and 7 are don't cares.

Doing the same for the other bits gives $T_0 = 1$ (the lowest bit changes at every pulse), $T_1 = Q_2'Q_0$ (it toggles in states 1 and 3), and $T_2 = Q_1Q_0 + Q_2Q_0$ from the map.

Worked examples

#include <stdio.h>
 
/* synchronous mod-6 counter with T flip-flops: T0 = 1, T1 = Q2' Q0, T2 = Q1 Q0 + Q2 Q0 */
static int mod6_next(int s) {
    int q2 = (s >> 2) & 1, q1 = (s >> 1) & 1, q0 = s & 1;
    int t0 = 1, t1 = !q2 && q0, t2 = (q1 && q0) || (q2 && q0);
    return s ^ (t2 << 2 | t1 << 1 | t0);
}
 
/* synchronous decade counter: T0 = 1, T1 = Q3' Q0, T2 = Q1 Q0, T3 = Q2 Q1 Q0 + Q3 Q0 */
static int mod10_next(int s) {
    int q3 = (s >> 3) & 1, q2 = (s >> 2) & 1, q1 = (s >> 1) & 1, q0 = s & 1;
    int t0 = 1, t1 = !q3 && q0, t2 = q1 && q0, t3 = (q2 && q1 && q0) || (q3 && q0);
    return s ^ (t3 << 3 | t2 << 2 | t1 << 1 | t0);
}
 
int main(void) {
    int s = 0;
    printf("mod-6:");
    for (int i = 0; i < 8; i++) {
        printf(" %d", s);
        s = mod6_next(s);
    }
    printf("\nunused states: 6 -> %d, 7 -> %d\n", mod6_next(6), mod6_next(7));
    s = 0;
    printf("mod-10:");
    for (int i = 0; i < 12; i++) {
        printf(" %d", s);
        s = mod10_next(s);
    }
    printf("\n");
    int j = 0;
    printf("Johnson, 3 stages:");
    for (int i = 0; i < 7; i++) {
        printf(" %d%d%d", (j >> 2) & 1, (j >> 1) & 1, j & 1);
        int in = !(j & 1);
        j = (j >> 1) | (in << 2);
    }
    printf("\nring, 4 stages:");
    int r = 8;
    for (int i = 0; i < 5; i++) {
        printf(" %d%d%d%d", (r >> 3) & 1, (r >> 2) & 1, (r >> 1) & 1, r & 1);
        r = ((r >> 1) | ((r & 1) << 3)) & 15;
    }
    printf("\n");
    double tpd = 10.0;
    printf("4-stage ripple counter, delay %.0f ns per stage: fmax about %.1f MHz\n", tpd, 1000.0 / (4 * tpd));
    return 0;
}

mod-6: 0 1 2 3 4 5 0 1
unused states: 6 -> 7, 7 -> 2
mod-10: 0 1 2 3 4 5 6 7 8 9 0 1
Johnson, 3 stages: 000 100 110 111 011 001 000
ring, 4 stages: 1000 0100 0010 0001 1000
4-stage ripple counter, delay 10 ns per stage: fmax about 25.0 MHz

Cheat box

Traps and GATE patterns

Connections

A counter is a special case of a state machine whose next state does not depend on any input. A ring or Johnson counter is a shift register with feedback. The input equations come from the excitation table and are minimised with a K-map. The program counter of the instruction cycle is a loadable counter.

PYQs

Consider a 2-bit saturating up/down counter that
performs the saturating up count when the input P
is 0, and the saturating down count when P is 1. The
Next State table of the counter is as shown. The
counter is built as a synchronous sequential circuit
using D flip-flops.

Input
Current
State
Next
State
P
Q1
Q1
+
Q0
+
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
1
1
1
1
0

Consider the given sequential circuit designed
using D-Flip-flops. The circuit is initialized with
some value (initial state). The number of distinct
states the circuit will go through before returning to
the initial state is . (Answer in integer)

In a 4-bit ripple counter, if the period of the waveform
at the last flip-flop is 64 microseconds, then the
frequency of the ripple counter in kHz is ________.
(Answer in integer)

Consider a sequential digital circuit consisting of T
flip-flops and D flip-flops as shown in the figure.
CLKIN is the clock input to the circuit. At the
beginning, Q1, Q2 and Q3 have values 0, 1 and 1,
respectively. Which one of the given values of (Q1,
Q2, Q3) can NEVER be obtained with this digital
circuit?

Consider a 3-bit counter, designed using T flip-flops,
as shown below :

Assuming the initial state of the counter given by
PQR as 000, what are the next three states?

The next state table of a 2-bit saturating up-counter is
given below.
Q1 Q0 Q1
+ Q0
+
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1

DIGITAL LOGIC

The counter is built as a synchronous sequential
circuit using T flip-flops. The expressions for T1
and T0 are

We want to design a synchronous counter that
counts the sequence 0-1-0-2-0-3 and then repeats.
The minimum number of J-K flip-flops required to
implement this counter is __________.

Consider a 4-bit Johnson counter with an initial value
of 0000. The counting sequence of this counter is

Let k = 2n. A circuit is built by giving the output of
an n-bit binary counter as input to an n-to-2n bit
decoder. This circuit is equivalent to a ?

The minimum number of D flip-flops needed to
design a mod-258 counter is

Consider the following circuit involving three D-
type flip-flops used in a certain type of counter
configuration

If at some instance prior to the occurrence of the
clock edge, and have a value , and respectively,
what shall be the value of after the clock edge?

In the sequential circuit shown below, if the initial
value of the output is . What are the next four values
of ?

The control signal functions of a - binary counter are
given below (where is "don't care"):

DIGITAL LOGIC

Assume that the counter and gate delays are
negligible. If the counter starts at then it cycles
through the following sequence

Self-check

Revision card

References