Latches and flip-flops

Why it exists

A combinational circuit forgets: change the inputs and the old output is gone. Anything that remembers, a register, a counter, the program counter, a finite-state controller, needs a circuit that stores a bit. The basic trick is feedback: connect two gates so that each one's output is the other's input. The loop has two stable states, and it stays in whichever one it was put in. From that single idea come the latch, the flip-flop, and every sequential circuit that follows. GATE asks for the behaviour tables, the characteristic equations, the output waveform for a given clock and input, the difference between a latch and a flip-flop, and the cause of the race-around condition.

Prerequisites

You need the gates of logic gates, in particular NAND and NOR.

Precise definitions

Sequential circuit. A circuit whose outputs depend on the present inputs and on stored state. It is synchronous if the state changes only at the ticks of a clock, and asynchronous otherwise. With $n$ storage elements it has up to $2^n$ states.

Latch and flip-flop. A latch is level sensitive: while its enable input is active the output follows the data input (it is transparent), and when the enable is inactive it holds. A flip-flop is edge triggered: it looks at its inputs only at a clock edge (rising or falling) and holds the value for the rest of the cycle. In symbols a small triangle on the clock input marks edge triggering, and a bubble before it marks the falling edge.

SR latch (NOR). Two cross-coupled NOR gates: $Q = (R + Q')'$ and $Q' = (S + Q)'$.

When $S = R = 1$ both outputs are forced to 0, so $Q$ and $Q'$ are no longer complements. If both inputs then return to 0 together the latch races: both gates change at the same moment and the final state is unpredictable. That is why $S = R = 1$ is forbidden.

SR latch (NAND). With cross-coupled NAND gates the inputs are active low: $S' = 0$ sets, $R' = 0$ resets, $S' = R' = 1$ holds and $S' = R' = 0$ is forbidden (both outputs 1).

Gated SR latch. Two extra gates make the inputs effective only while an enable $E$ is 1: $S_{eff} = S\,E$ and $R_{eff} = R\,E$.

D latch. A gated SR latch with $S = D$ and $R = D'$, so $S = R = 1$ cannot occur. While $E = 1$ the output follows $D$ (transparent), while $E = 0$ it holds. It can be built from four NAND gates: $N_1 = (DE)'$, $N_2 = (E N_1)'$, $Q = (N_1 Q')'$, $Q' = (N_2 Q)'$.

D flip-flop (edge triggered). Two D latches back to back, the first (master) transparent while the clock is low and the second (slave) transparent while the clock is high. At the rising edge the master closes holding the value $D$ had just before the edge, and the slave opens and passes it to the output. So $Q$ takes the value of $D$ at the rising edge and holds it for a whole cycle. A direct gate-level version uses six NAND gates (three SR latches). The characteristic equation is $Q^+ = D$ (here $Q$ is the present state and $Q^+$ the next state).

JK flip-flop. Behaves like an SR flip-flop with the forbidden input given a useful meaning:

Characteristic equation: $Q^+ = JQ' + K'Q$.

T flip-flop. Toggles when $T = 1$ and holds when $T = 0$: $Q^+ = T \oplus Q = TQ' + T'Q$. With $T = 1$ it divides the clock frequency by 2.

SR flip-flop. $Q^+ = S + R'Q$ with the restriction $SR = 0$.

Race-around. A JK latch (level triggered) with $J = K = 1$ toggles over and over for as long as the clock stays high, once per gate delay around the feedback loop, so the output at the end of the pulse depends on the pulse width. Master-slave or edge-triggered construction removes the problem: the output changes only once per clock.

Timing parameters. Setup time $t_{su}$: the data must be stable this long before the active clock edge. Hold time $t_h$: it must stay stable this long after the edge. Clock-to-output delay $t_{cq}$: the time from the edge until $Q$ is valid. If setup or hold is violated the flip-flop may enter a metastable state, an intermediate output that takes an unpredictable time to resolve.

Asynchronous inputs. Preset (set) and clear (reset) inputs force the output directly, independent of the clock.

How it works

Three animations show how the same ideas look in time. First the SR latch built from two NOR gates, with every output change one gate delay behind its cause. Watch the forbidden case at the end.

Next, a D latch and a D flip-flop driven by the same clock and the same data. The latch follows $D$ whenever the clock is high; the flip-flop changes only at the rising edge and takes the value $D$ had just before it.

With $J = K = 1$ a level-triggered JK latch toggles repeatedly during the high phase (race-around), while an edge-triggered one toggles once per clock.

The characteristic equation of the JK flip-flop is just the four rows of its table folded into one expression:

Worked examples

#include <stdio.h>
 
/* NOR-gate SR latch: update both gates until nothing changes */
static void sr_latch(int *q, int *qn, int s, int r) {
    for (int i = 0; i < 10; i++) {
        int q2 = !(r || *qn);
        int qn2 = !(s || *q);
        if (q2 == *q && qn2 == *qn) break;
        *q = q2;
        *qn = qn2;
    }
}
 
static int jk_next(int q, int j, int k) { return (j && !q) || (!k && q); }
 
int main(void) {
    printf("Q S R | Q+ Q'+\n");
    for (int q0 = 0; q0 < 2; q0++)
        for (int s = 0; s < 2; s++)
            for (int r = 0; r < 2; r++) {
                int q = q0, qn = !q0;
                sr_latch(&q, &qn, s, r);
                printf("%d %d %d |  %d  %d%s\n", q0, s, r, q, qn, s && r ? "   forbidden" : "");
            }
    int q = 0;
    int js[] = {1, 1, 0, 0, 1, 1}, ks[] = {0, 1, 0, 1, 0, 1};
    printf("JK sequence from Q = 0:");
    for (int i = 0; i < 6; i++) {
        q = jk_next(q, js[i], ks[i]);
        printf(" %d", q);
    }
    printf("\n");
    int t = 0;
    printf("T = 1 for eight clocks:");
    for (int i = 0; i < 8; i++) {
        t = t ^ 1;
        printf(" %d", t);
    }
    printf("\n");
    return 0;
}

Q S R | Q+ Q'+
0 0 0 |  0  1
0 0 1 |  0  1
0 1 0 |  1  0
0 1 1 |  0  0   forbidden
1 0 0 |  1  0
1 0 1 |  0  1
1 1 0 |  1  0
1 1 1 |  0  0   forbidden
JK sequence from Q = 0: 1 0 0 0 1 0
T = 1 for eight clocks: 1 0 1 0 1 0 1 0

Cheat box

Traps and GATE patterns

Connections

Conversions between the four flip-flop types are the next topic (flip-flop conversion). Rows of D flip-flops are registers and shift registers, T flip-flops chained are counters, and flip-flops plus combinational logic are state machines. In the processor, registers in the datapath and the control state are exactly these elements, and the clock period limit comes from $t_{cq}$ + logic delay + $t_{su}$ (see the instruction cycle).

PYQs

The output of a 2-input multiplexer is connected back
to one of its inputs as shown in the figure.

Match the functional equivalence of this circuit to
one of the following options

The next state table of a 2-bit saturating up-counter is
given below.
Q1 Q0 Q1
+ Q0
+
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1

DIGITAL LOGIC

The counter is built as a synchronous sequential
circuit using T flip-flops. The expressions for T1
and T0 are

Consider a combination of T and D flip-flops
connected as shown below. The output of the D
flip-flop is connected to the input of the T flip-flop
and the output of the T flip-flop is connected to the
input of the D flip-flop. Initially, both Q0 and Q1
are set to 1 (before the 1st clock cycle). The outputs

A positive edge-triggered D flip-flop is connected to
a positive edge-triggered JK flipflop as follows. The
Q output of the D flip-flop is connected to both the J
and K inputs of the JK flip-flop, while the Q output
of the JK flip-flop is connected to the input of the D
flip-flop. Initially, the output of the D flip-flop is set
to logic one and the output of the JK flip-flop is
cleared. Which one of the following is the bit
sequence (including the initial state) generated at the
Q output of the JK flip-flop when the flip-flops are
connected to a free-running common clock? Assume
that J = K = 1 is the toggle mode and J = K = 0 is the
state-holding mode of the JK flip-flop. Both the flip-
flops have non-zero propagation delays.

The above synchronous sequential circuit built
using JK flip-flops is initialized with Q2Q1Q0 = 000.
The state sequence for this circuit for the next 3
clock cycles is

You are given a free running clock with a duty
cycle of 50% and a digital waveform f which
changes only at the negative edge of the clock.
Which one of the following circuits (using clocked
D flip-flops) will delay the phase of f by 180°?

Consider the following circuit involving a positive
edge triggered D FF.

Consider the following timing diagram. Let
represents the logic level on the line in the -th clock
period

Let represent the complement of . The correct
output sequence on over the clock periods through
is:

Self-check

Revision card

References