Excitation tables and flip-flop conversion
The excitation table of each flip-flop type (which inputs produce a wanted transition), and the procedure for building one type from another, with all twelve conversions derived and checked.
Why it exists
The four flip-flop types (SR, D, JK, T) are interchangeable in function but not in the logic they need around them. A counter is simplest with T flip-flops, a register with D flip-flops, a general state machine is easy to derive with JK. Parts are sold in a few types, so a designer often has one type and needs another. The same table, the excitation table, is also the heart of the design procedure for counters and state machines on the following pages. GATE asks for the excitation table entries, which inputs convert one flip-flop to another, and how many gates a conversion needs.
Prerequisites
You need the characteristic tables and equations of the four types from latches and flip-flops, and don't care minimisation from Karnaugh maps.
Precise definitions
Characteristic equations (the next state from the present state and the inputs).
| Type | |
|---|---|
| SR | , with |
| JK | |
| D | |
| T |
Excitation table. The reverse question: given the present state and the required next state , which inputs achieve it? An X means the input can be 0 or 1 (a don't care).
| SR: | JK: | D: | T: | ||
|---|---|---|---|---|---|
| 0 | 0 | 0 X | 0 X | 0 | 0 |
| 0 | 1 | 1 0 | 1 X | 1 | 1 |
| 1 | 0 | 0 1 | X 1 | 0 | 1 |
| 1 | 1 | X 0 | X 0 | 1 | 0 |
Why the X entries appear: to stay at 0 a JK flip-flop may have (hold) or (reset), so is free; to go from 0 to 1 it may have (set) or (toggle), so is free; and symmetrically for when starting from 1.
Conversion procedure. To build a flip-flop of wanted type from one of the available type:
- Write a table with the wanted flip-flop's inputs and the present state , and fill in the required next state from the wanted characteristic equation.
- For each row, read the available flip-flop's required inputs from its excitation table (using the transition ).
- Treat the X entries (and any input combination that is illegal for the wanted type, such as ) as don't cares and minimise each available input as a function of the wanted inputs and with a Karnaugh map.
- Draw the logic that makes those inputs from the wanted inputs and the flip-flop's own and .
The twelve conversions (each derived by the procedure and checked on every state and legal input):
| Available | Wanted | Inputs of the available flip-flop |
|---|---|---|
| JK | T | |
| JK | D | , |
| JK | SR | , |
| D | T | |
| D | JK | |
| D | SR | |
| T | D | |
| T | JK | |
| T | SR | |
| SR | D | , |
| SR | JK | , |
| SR | T | , |
Two patterns to remember: a JK flip-flop needs no extra gates to act as T (tie the inputs together), and a T or D flip-flop converts to any other type with the characteristic equation of the wanted type: of the wanted flip-flop, and .
How it works
Convert an SR flip-flop into a JK flip-flop. Follow the table for the wanted JK () and read and from the SR excitation table:
| 0 | 0 | 0 | 0 | 0 | X |
| 0 | 0 | 1 | 1 | X | 0 |
| 0 | 1 | 0 | 0 | 0 | X |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | X | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
The two K-maps below minimise and using the X entries as don't cares.
SR flip-flop used as a JK: the S input as a function of J, K and Q: Fill in the map
Exact minimiser, not typed| J\KQ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 00 | X1 | 03 | 02 |
| 1 | 14 | X5 | 07 | 16 |
Small number = minterm index. X = don't care. Row and column labels are in Gray-code order.
Groups so far (product terms)
None yet.
Step 1
Rows are J, columns are KQ. S must be 1 only when the JK flip-flop has to go from 0 to 1 (J = 1 with Q = 0). When Q is already 1 and has to stay 1, S may be anything (a don't care), which is the X entries of the excitation table.
SR flip-flop used as a JK: the R input as a function of J, K and Q: Fill in the map
Exact minimiser, not typed| J\KQ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X0 | 01 | 13 | X2 |
| 1 | 04 | 05 | 17 | 06 |
Small number = minterm index. X = don't care. Row and column labels are in Gray-code order.
Groups so far (product terms)
None yet.
Step 1
R must be 1 only when the flip-flop has to go from 1 to 0 (K = 1 with Q = 1). When Q is 0 and has to stay 0, R is a don't care.
The result is and : set the SR flip-flop only when and the flip-flop is 0, and reset it only when and it is 1. Feeding and back like this is what prevents ever happening.
Worked examples
EX 1All twelve conversions in a program
EasyThe program implements each conversion from the table above and checks it against the wanted flip-flop for every state and every legal input combination (it skips for the SR type).
#include <stdio.h>
enum { SR, JK, D, T };
static const char *name[] = { "SR", "JK", "D", "T" };
static int next_state(int type, int q, int a, int b) {
switch (type) {
case SR: return a || (!b && q);
case JK: return (a && !q) || (!b && q);
case D: return a;
default: return a ^ q;
}
}
/* the two inputs (a, b) of the available flip-flop, as functions of the desired flip-flop's inputs (x, y) and Q */
static void conv(int avail, int want, int x, int y, int q, int *a, int *b) {
*b = 0;
if (avail == JK && want == T) { *a = x; *b = x; }
else if (avail == JK && want == D) { *a = x; *b = !x; }
else if (avail == JK && want == SR) { *a = x; *b = y; }
else if (avail == D && want == T) *a = x ^ q;
else if (avail == D && want == JK) *a = (x && !q) || (!y && q);
else if (avail == D && want == SR) *a = x || (!y && q);
else if (avail == T && want == D) *a = x ^ q;
else if (avail == T && want == JK) *a = (x && !q) || (y && q);
else if (avail == T && want == SR) *a = (x && !q) || (y && q);
else if (avail == SR && want == D) { *a = x; *b = !x; }
else if (avail == SR && want == JK) { *a = x && !q; *b = y && q; }
else if (avail == SR && want == T) { *a = x && !q; *b = x && q; }
else *a = 0;
}
int main(void) {
int total = 0, pairs = 0;
for (int avail = 0; avail < 4; avail++)
for (int want = 0; want < 4; want++) {
if (avail == want) continue;
int bad = 0;
for (int x = 0; x < 2; x++)
for (int y = 0; y < 2; y++)
for (int q = 0; q < 2; q++) {
if (want == SR && x && y) continue;
if ((want == D || want == T) && y) continue;
int a, b;
conv(avail, want, x, y, q, &a, &b);
bad += next_state(avail, q, a, b) != next_state(want, q, x, y);
}
pairs++;
total += bad;
if (bad) printf("%s as %s: %d wrong\n", name[avail], name[want], bad);
}
printf("%d conversions checked, %d wrong rows\n", pairs, total);
int q = 0;
printf("T built from D (D = T xor Q), T = 1 five times:");
for (int i = 0; i < 5; i++) {
int a, b;
conv(D, T, 1, 0, q, &a, &b);
q = next_state(D, q, a, b);
printf(" %d", q);
}
printf("\n");
return 0;
}12 conversions checked, 0 wrong rows
T built from D (D = T xor Q), T = 1 five times: 1 0 1 0 1The last line shows a T flip-flop made from a D flip-flop, , with : the output toggles at every clock, as a T flip-flop does.
EX 2JK as T and as D
EasyJK as T. The T flip-flop toggles () or holds (). The JK flip-flop holds at and toggles at , so connect .
JK as D. The D flip-flop sets when and resets when . The JK flip-flop sets at and resets at , so connect and (one inverter).
EX 3D as T and as JK
MediumD as T. The wanted next state is , and a D flip-flop copies , so (one XOR gate).
D as JK. The wanted next state is , so . Gates: two ANDs, one OR and an inverter for ( comes from the flip-flop), 4 gates.
EX 4T as D and T as JK
MediumFor a T flip-flop the required input is the difference . T as D: , so . T as JK: , so . Case by case: for the next state is and ; for the next state is and ; hence .
EX 5Count the gates of a conversion
GATE levelAssume and are both available and the wanted inputs come in true form only.
| Conversion | Gates |
|---|---|
| JK as T | 0 |
| JK as D | 1 (inverter) |
| D as T | 1 (XOR) |
| SR as D | 1 (inverter) |
| SR as T | 2 (two ANDs) |
| SR as JK | 2 (two ANDs) |
| T as JK | 3 (two ANDs and an OR) |
| D as JK | 4 (two ANDs, an OR and an inverter for ) |
(Each count assumes the simplest form from the table; a question may count an XOR as several gates.)
EX 6Which input values does the flip-flop need for this transition?
GATE levelA JK flip-flop must go from to . The excitation table gives , : reset with or toggle with . A T flip-flop needs . A D flip-flop needs . An SR flip-flop needs and .
For the transition : SR needs , free; JK needs , free; D needs ; T needs .
Cheat box
Cheat box
- Excitation table: : SR , JK , D 0, T 0. : SR , JK , D 1, T 1. : SR , JK , D 0, T 1. : SR , JK , D 1, T 0.
- Procedure: wanted characteristic table, then available excitation table, then K-map with X as don't cares.
- JK as T: . JK as D: , .
- D as T: . D as JK: . T as D: . T as JK: .
- SR as JK: , . SR as D: , . SR as T: , .
- For a D flip-flop . For a T flip-flop .
Traps and GATE patterns
Connections
Builds on
Across subjects
No cross-subject links yet.
The excitation table is the central tool when designing counters and state machines: the flip-flop input equations are exactly the excitation of the required state transitions. Registers use the D flip-flop because its excitation is trivial, see registers and shift registers. The simplification step is the K-map with don't cares.
PYQs
1 previous year question from your book. I re-solved each one myself (1 by running or simulating, 0 by reasoning only); the book's key is shown next to my answer. All PYQs
Consider a 3-bit counter, designed using T flip-flops, as shown below : Assuming the initial state of the counter given by PQR as 000, what are the next three states?
- (a)001, 010, 111
- (b)011, 101, 000
- (c)001, 010, 000
- (d)011, 101, 111
Self-check
Question 1
A D flip-flop is connected with . What does it do?
Show answerHide
: it toggles at every clock edge, the same as a T flip-flop with (and it divides the clock frequency by 2).
Question 2
Which JK input values give the transition to ?
Show answerHide
and is a don't care: (set) or (toggle).
Question 3
What are in terms of and for a T flip-flop used as a D flip-flop?
Show answerHide
: toggle only when the wanted next state differs from the present state .
Question 4
An SR flip-flop is built from a JK flip-flop with , . What happens when ?
Show answerHide
The JK flip-flop toggles, so the converted device does not have a forbidden state (it gives a defined output). This is the JK flip-flop's improvement over SR.
Revision card
One-screen revision
- Excitation: JK : ; : ; : ; : . T = , D = .
- Conversion = wanted characteristic table, then available excitation table, then K-map with don't cares.
- JK T: . JK D: , . D T: . SR JK: , .
- D with toggles every clock.
References
- ·Mano and Ciletti, Digital Design, 5th ed., Chapter 5 Synchronous Sequential Logic (flip-flop excitation tables, design procedure)
- ·Kohavi and Jha, Switching and Finite Automata Theory, Chapter on sequential circuit design
Verification
The characteristic and excitation tables are enumerated and each of the twelve conversions is derived by the exact minimiser (with the excitation don't cares) and then simulated for every state and legal input in scripts/enum-checks/dl_seq.py; the C program re-checks all twelve. The two K-map animations are produced by the exact minimiser and re-derived in tests/dl-traces.test.ts. Textbook chapter titles are from memory; the independent second pass has not been run, so the page stays draft. SECOND PASS (2026-11-02, done by the assistant, not a human check): every Self-check question was solved before the printed answer was read and all agreed; the definitions, worked examples, cheat box and traps were read claim by claim and the numbers re-derived by hand or by a small script (conversions, signed ranges and flags, IEEE 754 fields and custom formats, Boolean identities and counts, K-map groups, adder carries, BCD correction, flip-flop conversions, counter sequences and T equations, state reduction, Quine-McCluskey rounds and covers, floating-point alignment and rounding); long C programs were not re-read line by line (they are compiled and compared by npm run verify:c, and their printed outputs were checked against the prose); tables and animations are machine output and were read, not re-run; No other defect found. Status raised to self-checked; verified needs a textbook or human check.
last verified: never
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