G27
Self-checkedTier 1 14 min readdl.flipflop-conversion

Excitation tables and flip-flop conversion

The excitation table of each flip-flop type (which inputs produce a wanted transition), and the procedure for building one type from another, with all twelve conversions derived and checked.

Why it exists

The four flip-flop types (SR, D, JK, T) are interchangeable in function but not in the logic they need around them. A counter is simplest with T flip-flops, a register with D flip-flops, a general state machine is easy to derive with JK. Parts are sold in a few types, so a designer often has one type and needs another. The same table, the excitation table, is also the heart of the design procedure for counters and state machines on the following pages. GATE asks for the excitation table entries, which inputs convert one flip-flop to another, and how many gates a conversion needs.

Prerequisites

You need the characteristic tables and equations of the four types from latches and flip-flops, and don't care minimisation from Karnaugh maps.

Precise definitions

Characteristic equations (the next state Q+Q^+ from the present state QQ and the inputs).

TypeQ+Q^+
SRS+R′QS + R'Q, with SR=0SR = 0
JKJQ′+K′QJQ' + K'Q
DDD
TT⊕Q=TQ′+T′QT \oplus Q = TQ' + T'Q

Excitation table. The reverse question: given the present state QQ and the required next state Q+Q^+, which inputs achieve it? An X means the input can be 0 or 1 (a don't care).

QQQ+Q^+SR: S RS\,RJK: J KJ\,KD: DDT: TT
000 X0 X00
011 01 X11
100 1X 101
11X 0X 010

Why the X entries appear: to stay at 0 a JK flip-flop may have JK=00J K = 00 (hold) or 0101 (reset), so KK is free; to go from 0 to 1 it may have JK=10JK = 10 (set) or 1111 (toggle), so KK is free; and symmetrically for JJ when starting from 1.

Conversion procedure. To build a flip-flop of wanted type from one of the available type:

  1. Write a table with the wanted flip-flop's inputs and the present state QQ, and fill in the required next state Q+Q^+ from the wanted characteristic equation.
  2. For each row, read the available flip-flop's required inputs from its excitation table (using the transition Q→Q+Q \to Q^+).
  3. Treat the X entries (and any input combination that is illegal for the wanted type, such as S=R=1S = R = 1) as don't cares and minimise each available input as a function of the wanted inputs and QQ with a Karnaugh map.
  4. Draw the logic that makes those inputs from the wanted inputs and the flip-flop's own QQ and Q′Q'.

The twelve conversions (each derived by the procedure and checked on every state and legal input):

AvailableWantedInputs of the available flip-flop
JKTJ=K=TJ = K = T
JKDJ=DJ = D, K=D′K = D'
JKSRJ=SJ = S, K=RK = R
DTD=T⊕Q=T′Q+TQ′D = T \oplus Q = T'Q + TQ'
DJKD=JQ′+K′QD = JQ' + K'Q
DSRD=S+R′QD = S + R'Q
TDT=D⊕Q=D′Q+DQ′T = D \oplus Q = D'Q + DQ'
TJKT=JQ′+KQT = JQ' + KQ
TSRT=SQ′+RQT = SQ' + RQ
SRDS=DS = D, R=D′R = D'
SRJKS=JQ′S = JQ', R=KQR = KQ
SRTS=TQ′S = TQ', R=TQR = TQ

Two patterns to remember: a JK flip-flop needs no extra gates to act as T (tie the inputs together), and a T or D flip-flop converts to any other type with the characteristic equation of the wanted type: D=Q+D = Q^+ of the wanted flip-flop, and T=Q⊕Q+T = Q \oplus Q^+.

How it works

Convert an SR flip-flop into a JK flip-flop. Follow the table for the wanted JK (Q+=JQ′+K′QQ^+ = JQ' + K'Q) and read SS and RR from the SR excitation table:

JJKKQQQ+Q^+SSRR
00000X
0011X0
01000X
011001
100110
1011X0
110110
111001

The two K-maps below minimise SS and RR using the X entries as don't cares.

SR flip-flop used as a JK: the S input as a function of J, K and Q: Fill in the map

Exact minimiser, not typed
J\KQ00011110
000X10302
114X50716

Small number = minterm index. X = don't care. Row and column labels are in Gray-code order.

Groups so far (product terms)

None yet.

Step 1

Rows are J, columns are KQ. S must be 1 only when the JK flip-flop has to go from 0 to 1 (J = 1 with Q = 0). When Q is already 1 and has to stay 1, S may be anything (a don't care), which is the X entries of the excitation table.

1 / 3
computed by script: exact integer, Fraction and truth-table evaluation (IEEE 754 patterns via Python struct where used), not typed by hand. python3 scripts/gen-dl-traces.py

SR flip-flop used as a JK: the R input as a function of J, K and Q: Fill in the map

Exact minimiser, not typed
J\KQ00011110
0X00113X2
104051706

Small number = minterm index. X = don't care. Row and column labels are in Gray-code order.

Groups so far (product terms)

None yet.

Step 1

R must be 1 only when the flip-flop has to go from 1 to 0 (K = 1 with Q = 1). When Q is 0 and has to stay 0, R is a don't care.

1 / 3
computed by script: exact integer, Fraction and truth-table evaluation (IEEE 754 patterns via Python struct where used), not typed by hand. python3 scripts/gen-dl-traces.py

The result is S=JQ′S = JQ' and R=KQR = KQ: set the SR flip-flop only when J=1J = 1 and the flip-flop is 0, and reset it only when K=1K = 1 and it is 1. Feeding QQ and Q′Q' back like this is what prevents S=R=1S = R = 1 ever happening.

Worked examples

EX 1All twelve conversions in a program

Easy

The program implements each conversion from the table above and checks it against the wanted flip-flop for every state and every legal input combination (it skips S=R=1S = R = 1 for the SR type).

#include <stdio.h>
 
enum { SR, JK, D, T };
static const char *name[] = { "SR", "JK", "D", "T" };
 
static int next_state(int type, int q, int a, int b) {
    switch (type) {
    case SR: return a || (!b && q);
    case JK: return (a && !q) || (!b && q);
    case D: return a;
    default: return a ^ q;
    }
}
 
/* the two inputs (a, b) of the available flip-flop, as functions of the desired flip-flop's inputs (x, y) and Q */
static void conv(int avail, int want, int x, int y, int q, int *a, int *b) {
    *b = 0;
    if (avail == JK && want == T) { *a = x; *b = x; }
    else if (avail == JK && want == D) { *a = x; *b = !x; }
    else if (avail == JK && want == SR) { *a = x; *b = y; }
    else if (avail == D && want == T) *a = x ^ q;
    else if (avail == D && want == JK) *a = (x && !q) || (!y && q);
    else if (avail == D && want == SR) *a = x || (!y && q);
    else if (avail == T && want == D) *a = x ^ q;
    else if (avail == T && want == JK) *a = (x && !q) || (y && q);
    else if (avail == T && want == SR) *a = (x && !q) || (y && q);
    else if (avail == SR && want == D) { *a = x; *b = !x; }
    else if (avail == SR && want == JK) { *a = x && !q; *b = y && q; }
    else if (avail == SR && want == T) { *a = x && !q; *b = x && q; }
    else *a = 0;
}
 
int main(void) {
    int total = 0, pairs = 0;
    for (int avail = 0; avail < 4; avail++)
        for (int want = 0; want < 4; want++) {
            if (avail == want) continue;
            int bad = 0;
            for (int x = 0; x < 2; x++)
                for (int y = 0; y < 2; y++)
                    for (int q = 0; q < 2; q++) {
                        if (want == SR && x && y) continue;
                        if ((want == D || want == T) && y) continue;
                        int a, b;
                        conv(avail, want, x, y, q, &a, &b);
                        bad += next_state(avail, q, a, b) != next_state(want, q, x, y);
                    }
            pairs++;
            total += bad;
            if (bad) printf("%s as %s: %d wrong\n", name[avail], name[want], bad);
        }
    printf("%d conversions checked, %d wrong rows\n", pairs, total);
    int q = 0;
    printf("T built from D (D = T xor Q), T = 1 five times:");
    for (int i = 0; i < 5; i++) {
        int a, b;
        conv(D, T, 1, 0, q, &a, &b);
        q = next_state(D, q, a, b);
        printf(" %d", q);
    }
    printf("\n");
    return 0;
}
12 conversions checked, 0 wrong rows
T built from D (D = T xor Q), T = 1 five times: 1 0 1 0 1

The last line shows a T flip-flop made from a D flip-flop, D=T⊕QD = T \oplus Q, with T=1T = 1: the output toggles at every clock, as a T flip-flop does.

EX 2JK as T and as D

Easy

JK as T. The T flip-flop toggles (T=1T = 1) or holds (T=0T = 0). The JK flip-flop holds at JK=00JK = 00 and toggles at JK=11JK = 11, so connect J=K=TJ = K = T.

JK as D. The D flip-flop sets when D=1D = 1 and resets when D=0D = 0. The JK flip-flop sets at JK=10JK = 10 and resets at 0101, so connect J=DJ = D and K=D′K = D' (one inverter).

EX 3D as T and as JK

Medium

D as T. The wanted next state is Q+=T⊕QQ^+ = T \oplus Q, and a D flip-flop copies DD, so D=T⊕QD = T \oplus Q (one XOR gate).

D as JK. The wanted next state is Q+=JQ′+K′QQ^+ = JQ' + K'Q, so D=JQ′+K′QD = JQ' + K'Q. Gates: two ANDs, one OR and an inverter for KK (Q′Q' comes from the flip-flop), 4 gates.

EX 4T as D and T as JK

Medium

For a T flip-flop the required input is the difference T=Q⊕Q+T = Q \oplus Q^+. T as D: Q+=DQ^+ = D, so T=Q⊕DT = Q \oplus D. T as JK: Q+=JQ′+K′QQ^+ = JQ' + K'Q, so T=Q⊕(JQ′+K′Q)T = Q \oplus (JQ' + K'Q). Case by case: for Q=0Q = 0 the next state is JJ and T=JT = J; for Q=1Q = 1 the next state is K′K' and T=KT = K; hence T=JQ′+KQT = JQ' + KQ.

EX 5Count the gates of a conversion

GATE level

Assume QQ and Q′Q' are both available and the wanted inputs come in true form only.

ConversionGates
JK as T0
JK as D1 (inverter)
D as T1 (XOR)
SR as D1 (inverter)
SR as T2 (two ANDs)
SR as JK2 (two ANDs)
T as JK3 (two ANDs and an OR)
D as JK4 (two ANDs, an OR and an inverter for KK)

(Each count assumes the simplest form from the table; a question may count an XOR as several gates.)

EX 6Which input values does the flip-flop need for this transition?

GATE level

A JK flip-flop must go from Q=1Q = 1 to Q+=0Q^+ = 0. The excitation table gives J=XJ = X, K=1K = 1: reset with JK=01JK = 01 or toggle with JK=11JK = 11. A T flip-flop needs T=1T = 1. A D flip-flop needs D=0D = 0. An SR flip-flop needs S=0S = 0 and R=1R = 1.

For the transition 0→00 \to 0: SR needs S=0S = 0, RR free; JK needs J=0J = 0, KK free; D needs D=0D = 0; T needs T=0T = 0.

Cheat box

Cheat box

  • Excitation table: 0→00 \to 0: SR 0X0X, JK 0X0X, D 0, T 0. 0→10 \to 1: SR 1010, JK 1X1X, D 1, T 1. 1→01 \to 0: SR 0101, JK X1X1, D 0, T 1. 1→11 \to 1: SR X0X0, JK X0X0, D 1, T 0.
  • Procedure: wanted characteristic table, then available excitation table, then K-map with X as don't cares.
  • JK as T: J=K=TJ = K = T. JK as D: J=DJ = D, K=D′K = D'.
  • D as T: D=T⊕QD = T \oplus Q. D as JK: D=JQ′+K′QD = JQ' + K'Q. T as D: T=D⊕QT = D \oplus Q. T as JK: T=JQ′+KQT = JQ' + KQ.
  • SR as JK: S=JQ′S = JQ', R=KQR = KQ. SR as D: S=DS = D, R=D′R = D'. SR as T: S=TQ′S = TQ', R=TQR = TQ.
  • For a D flip-flop D=Q+D = Q^+. For a T flip-flop T=Q⊕Q+T = Q \oplus Q^+.

Traps and GATE patterns

Connections

The excitation table is the central tool when designing counters and state machines: the flip-flop input equations are exactly the excitation of the required state transitions. Registers use the D flip-flop because its excitation is trivial, see registers and shift registers. The simplification step is the K-map with don't cares.

PYQs

1 previous year question from your book. I re-solved each one myself (1 by running or simulating, 0 by reasoning only); the book's key is shown next to my answer. All PYQs

GATE 2021 · Set 1 · MCQQ7 · page 185 of the book
Consider a 3-bit counter, designed using T flip-flops,
as shown below :

Assuming the initial state of the counter given by
PQR as 000, what are the next three states?
  • (a)001, 010, 111
  • (b)011, 101, 000
  • (c)001, 010, 000
  • (d)011, 101, 111

Self-check

Question 1

A D flip-flop is connected with D=Q′D = Q'. What does it do?

Show answer

Q+=D=Q′Q^+ = D = Q': it toggles at every clock edge, the same as a T flip-flop with T=1T = 1 (and it divides the clock frequency by 2).

Question 2

Which JK input values give the transition Q=0Q = 0 to Q+=1Q^+ = 1?

Show answer

J=1J = 1 and KK is a don't care: JK=10JK = 10 (set) or 1111 (toggle).

Question 3

What are TT in terms of DD and QQ for a T flip-flop used as a D flip-flop?

Show answer

T=D⊕QT = D \oplus Q: toggle only when the wanted next state DD differs from the present state QQ.

Question 4

An SR flip-flop is built from a JK flip-flop with J=SJ = S, K=RK = R. What happens when S=R=1S = R = 1?

Show answer

The JK flip-flop toggles, so the converted device does not have a forbidden state (it gives a defined output). This is the JK flip-flop's improvement over SR.

Revision card

One-screen revision

  • Excitation: JK 0→00 \to 0: 0X0X; 0→10 \to 1: 1X1X; 1→01 \to 0: X1X1; 1→11 \to 1: X0X0. T = Q⊕Q+Q \oplus Q^+, D = Q+Q^+.
  • Conversion = wanted characteristic table, then available excitation table, then K-map with don't cares.
  • JK →\to T: J=K=TJ = K = T. JK →\to D: J=DJ = D, K=D′K = D'. D →\to T: D=T⊕QD = T \oplus Q. SR →\to JK: S=JQ′S = JQ', R=KQR = KQ.
  • D with D=Q′D = Q' toggles every clock.

References

  • ·Mano and Ciletti, Digital Design, 5th ed., Chapter 5 Synchronous Sequential Logic (flip-flop excitation tables, design procedure)
  • ·Kohavi and Jha, Switching and Finite Automata Theory, Chapter on sequential circuit design

Verification

The characteristic and excitation tables are enumerated and each of the twelve conversions is derived by the exact minimiser (with the excitation don't cares) and then simulated for every state and legal input in scripts/enum-checks/dl_seq.py; the C program re-checks all twelve. The two K-map animations are produced by the exact minimiser and re-derived in tests/dl-traces.test.ts. Textbook chapter titles are from memory; the independent second pass has not been run, so the page stays draft. SECOND PASS (2026-11-02, done by the assistant, not a human check): every Self-check question was solved before the printed answer was read and all agreed; the definitions, worked examples, cheat box and traps were read claim by claim and the numbers re-derived by hand or by a small script (conversions, signed ranges and flags, IEEE 754 fields and custom formats, Boolean identities and counts, K-map groups, adder carries, BCD correction, flip-flop conversions, counter sequences and T equations, state reduction, Quine-McCluskey rounds and covers, floating-point alignment and rounding); long C programs were not re-read line by line (they are compiled and compared by npm run verify:c, and their printed outputs were checked against the prose); tables and animations are machine output and were read, not re-run; No other defect found. Status raised to self-checked; verified needs a textbook or human check.

last verified: never