Self-checkedTier 1 15 min readcoa.interrupts

Interrupts and vectoring

Interrupt-driven I/O: the interrupt cycle step by step, maskable and non-maskable requests, interrupts versus traps and exceptions, how the source is identified (polling, vectored, daisy chain, parallel priority), priorities and nesting, latency and the CPU time an interrupt-driven device costs.

Why it exists

Polling makes the processor sit and ask. An interrupt reverses the roles: the device raises a signal when it needs service, and the processor, which has been doing useful work, suspends it, runs a short interrupt service routine (ISR) for the device and then carries on exactly where it left off. The same mechanism also handles events inside the processor itself (division by zero, a missing page) and system calls. GATE asks what happens during an interrupt and in which order, how the processor finds the right routine, how priority and nesting work, and how much CPU time an interrupt-driven device costs.

Prerequisites

I/O interface and programmed I/O

You need the picture of a device interface with a READY signal from I/O interface and programmed I/O, and the idea of the stack from stack frames (an interrupt saves the return address the way a call does).

Precise definitions

Interrupt. A signal that causes the processor to suspend the running program, save enough state to resume it, and transfer control to a service routine. After the routine finishes, execution resumes at the interrupted point.

Kinds of events (the vocabulary differs between books; this is the usual GATE reading).

External (hardware) interrupts, from devices, asynchronous to the instruction stream. A maskable interrupt (INTR) can be ignored by clearing the interrupt-enable flag. A non-maskable interrupt (NMI) cannot be masked and is used for events that must not be missed (power failure, memory parity error).
Internal events (traps, exceptions), caused by the instruction being executed, therefore synchronous: division by zero, arithmetic overflow, illegal opcode, privileged instruction in user mode, page fault. A fault is detected before the instruction completes and is restartable: the saved PC points at the faulting instruction, so it can be re-executed after the handler fixes the cause (the page fault is the standard case). A trap is reported after the instruction, with the saved PC pointing to the next one.
Software interrupts are deliberate: an instruction such as INT n or a system-call instruction invokes a routine through the same mechanism, and is how a user program asks the operating system for a service.

Interrupt cycle (the step added to the instruction cycle). At the end of each instruction the processor samples the request lines. If a request is pending and interrupts are enabled it does, in order:

finish the current instruction (the request does not stop it midway);
save the state: push the return address (the PC) and the processor status (flags) on the stack;
disable further interrupts (so the routine is not interrupted before it has saved what it needs; it may re-enable them);
identify the source and load the PC with the starting address of its service routine;
run the ISR, which saves any other registers it will change and restores them at the end;
execute the return-from-interrupt instruction, which restores the status and the PC from the stack, so the interrupted program continues.

Interrupt latency is the time from the request to the first instruction of the ISR: the remainder of the current instruction plus the hardware steps above. The cost of one interrupt is the latency plus the ISR plus the return.

Identifying the source (several devices share the processor).

Software polling. One INTR line; the ISR reads each device's status register in turn until it finds the one that is ready. The order of the polling is the priority. Simple, but slow.
Vectored interrupts. The device supplies a vector, a number or address, during the acknowledge cycle. The processor uses it as an index into the interrupt vector table in memory, whose entry holds the ISR's starting address. Entry address $=$ table base $+$ vector $\times$ entry size. No software search is needed.
Daisy chain (serial priority). The devices share one request line, and the acknowledge signal INTA goes from the processor to the first device and is passed from device to device. A device that is not requesting passes it on; a requesting device keeps it and puts its vector on the bus. Device order along the chain is the priority: the device nearest the processor has the highest priority. It needs few wires, but a distant device can be starved.
Parallel priority. Each device has its own request line. A priority encoder picks the highest-priority pending request, and a mask register can disable individual lines. It is faster and the priority can be changed in software by the mask, but needs more hardware.

Priority and nesting. Each source has a priority. A new request is accepted while an ISR runs only if its priority is higher than that of the routine now running (and interrupts are enabled); lower or equal requests wait. Because the saved state goes on the stack, handlers can nest to any depth the stack allows, and they finish in the reverse order of the nesting.

Interrupt versus subroutine call. A call happens at a point chosen by the programmer and saves only the return address; an interrupt can arrive between any two instructions, so it must save the status as well and the interrupted program cannot know it happened. The return address of an interrupt is the next instruction; for a call it is the instruction after the call.

How it works

The animation runs one interrupt on a small machine: the keyboard raises a request during an ADD, the CPU finishes the ADD and only then accepts it, pushes the PC and flags, disables interrupts, takes the vector, runs the ISR (which saves R0 because it needs it), and returns. At the end the main program's registers and stack are exactly as they would have been without the interrupt.

An interrupt: finish, save, vector, service, return: step 1

Machine run, not typed

start(main program running)

100

1000

IRQ

DEV

addr	decimal	meaning
064		main: ADD R0,#1	PC
065		main: ADD R0,#1
066		main: ADD R0,#1
004	200	vector table entry 4 (keyboard)
0C8		ISR: PUSH R0
0C9		ISR: IN R0,[DEV]
0CA		ISR: ST R0,[300]
0CB		ISR: POP R0
0CC		ISR: IRET
12C	.	input buffer
3E7	.	stack
3E6	.	stack
3E5	.	stack

Step 1

The main program is adding 1 to R0 (R0 = 5). The interrupt-enable flag I is 1, so interrupts are accepted. The stack grows downward from 1000. Entry 4 of the interrupt vector table holds the address of the keyboard routine (200). A key is about to be pressed: the keyboard will put its code (66) in its data register DEV and raise an interrupt request.

1 / 16

computed by script: a simulation of the machine or protocol, one event per step. python3 scripts/gen-coa-io-traces.py

The comparison of schemes, shown with the same device on a time axis, is on the previous page; the timeline for interrupt-driven I/O there has a three-tick ISR per word and gets 27 of 36 ticks of useful work.

Worked examples

EX 1What interrupts cost

Easy

A device delivers a 4-byte word at 1 MB/s. Each interrupt costs 20 cycles of latency and 100 cycles of service routine; the CPU runs at 500 MHz. Compare with polling the same device at 400 cycles per poll.

#include <stdio.h>
 
int main(void) {
    /* a device sends a 4-byte word at 1 MB/s; each interrupt costs 20 cycles of latency and 100 of service routine; CPU 500 MHz */
    double per_s = 1e6 / 4, cycles = 20 + 100, clock = 500e6;
    printf("%.0f interrupts/s, %.0f cycles each: %.1f%% of the CPU\n", per_s, cycles, 100.0 * per_s * cycles / clock);
    /* the same device polled with 400-cycle polls would cost */
    printf("polling the same device: %.1f%%\n", 100.0 * per_s * 400 / clock);
    return 0;
}

250000 interrupts/s, 120 cycles each: 6.0% of the CPU
polling the same device: 20.0%

Reading it. Interrupts per second $=$ rate $/$ unit $= 250\,000$ ; each costs 120 cycles, so $250\,000 \times 120 / (500 \times 10^6) = 0.06$ . Polling at the same rate costs more than three times as much (20% against 6%), because a poll costs more cycles than the interrupt work here. The comparison turns around when the device is rarely ready (see example 6).

EX 2Finding the service routine through the vector table

Easy

A processor with 4-byte vector table entries, the table starting at address 0, receives vector number $21_{16}$ .

#include <stdio.h>
 
int main(void) {
    unsigned base = 0x0000, entry = 4, vec = 0x21;
    printf("vector 0x%02X, %u-byte entries, table at 0x%04X: entry at 0x%04X\n", vec, entry, base, base + vec * entry);
    return 0;
}

vector 0x21, 4-byte entries, table at 0x0000: entry at 0x0084

Reading it. Entry address $= \text{base} + \text{vector} \times \text{entry size} = 0 + 33 \times 4 = 132 = 84_{16}$ . The four bytes there hold the address of the ISR. The vector is an index, not the address of the routine: the extra step lets the operating system change a routine by changing a table entry.

EX 3Which device does the daisy chain serve?

Medium

Four devices, numbered 0 to 3 from the processor outwards, share a daisy chain. Devices 1 and 3 request at the same time.

#include <stdio.h>
 
/* four devices on a daisy chain; device 0 is nearest the CPU. The grant enters device 0 and is passed on only by devices that are NOT requesting. */
static int granted(unsigned req) {
    for (int d = 0; d < 4; d++)
        if (req >> d & 1) return d;
    return -1;
}
 
int main(void) {
    int ok = 1;
    for (unsigned req = 1; req < 16; req++) {
        int lowest = 0;
        while (!(req >> lowest & 1)) lowest++;
        ok = ok && granted(req) == lowest;
    }
    printf("grant always goes to the requesting device nearest the CPU: %d\n", ok);
    printf("requests {1,3} -> device %d; requests {2,3} -> device %d; none -> %d\n", granted(0xA), granted(0xC), granted(0));
    return 0;
}

grant always goes to the requesting device nearest the CPU: 1
requests {1,3} -> device 1; requests {2,3} -> device 2; none -> -1

Reading it. The acknowledge signal reaches device 1 first, device 1 is requesting, so it keeps the signal and device 3 never sees it until device 1 has been served. The rule holds for all 15 non-empty request patterns. Device 3 is served only when no closer device is requesting, which is how starvation of far devices can happen.

EX 4Nested interrupts with priorities

Medium

Three service routines: A (priority 2, runs 5 ticks) requested at tick 0, B (priority 3, 3 ticks) requested at tick 2, C (priority 1, 2 ticks) requested at tick 3. A higher number means a higher priority. When is each running?

#include <stdio.h>
 
struct job { char name; int prio, arrive, length; };
 
int main(void) {
    /* higher number = higher priority; a request preempts only a lower-priority handler */
    struct job j[3] = {{'A', 2, 0, 5}, {'B', 3, 2, 3}, {'C', 1, 3, 2}};
    int left[3] = {5, 3, 2};
    char line[13];
    for (int t = 0; t < 12; t++) {
        int best = -1;
        for (int i = 0; i < 3; i++)
            if (j[i].arrive <= t && left[i] > 0 && (best < 0 || j[i].prio > j[best].prio)) best = i;
        if (best < 0) line[t] = '-';
        else { line[t] = j[best].name; left[best]--; }
    }
    line[12] = 0;
    printf("tick 0..11: %s\n", line);
    return 0;
}

tick 0..11: AABBBAAACC--

Reading it. A starts alone. At tick 2 B arrives with a higher priority, so it interrupts A (A has 3 ticks left, saved on the stack). C arrives at tick 3 with a lower priority than B, so it must wait. B finishes at tick 5 and A resumes (the stack unwinds). C, still waiting, runs only after A finishes at tick 8. The main program gets the processor back at tick 10 (shown as -). The last-in first-out order of the saved states is why a stack is the natural place for them.

EX 5Interrupt, trap, or neither?

Medium

Classify these events by the convention above.

Event	Class	Synchronous?	Can it be masked?
A key is pressed	external (hardware) interrupt	no	yes (INTR)
Power is about to fail	external, non-maskable (NMI)	no	no
`x / 0` for an integer	internal exception	yes	no
A page is not in memory	internal fault (restartable)	yes	no
A program executes the system-call instruction	software interrupt	yes	no
A timer reaches 0	external interrupt	no	yes

Internal events are caused by the instruction being executed, so they cannot be masked away; only external requests on a maskable line can.

EX 6When is an interrupt cheaper than polling?

GATE level

Polling costs $c_p$ cycles per poll and the processor must poll at a rate $p$ polls per second to keep up; the device is ready in a fraction $f$ of the polls, so it produces $f \cdot p$ events per second. An interrupt costs $c_i$ cycles per event. Ignoring the work of moving the data (both schemes pay it equally), interrupts are cheaper when

$f\,p\,c_i < p\,c_p \iff f < \frac{c_p}{c_i}.$

With $c_p = 400$ and $c_i = 1200$ the break-even is $f = 1/3$ : if the device is ready in less than a third of the polls, interrupts win. For a keyboard (ready in a tiny fraction of polls) interrupts win by a large factor; for a disk that is ready on almost every poll, the saving disappears, which is why bulk devices use DMA.

Cheat box

Check for interrupts at the END of each instruction. Order: finish instruction, save PC and flags, disable interrupts, get vector, load PC, run ISR, restore, return.
Maskable (INTR) can be disabled; NMI cannot. Internal exceptions are synchronous and not maskable.
Vector entry address $=$ base $+$ vector $\times$ entry size; the entry holds the ISR address.
Daisy chain: nearest device = highest priority. Parallel priority: encoder plus mask register.
A new request interrupts a running ISR only if its priority is higher.
Cost per second $=$ events per second $\times$ (latency $+$ ISR $+$ return) cycles $/$ clock.
Fault: saved PC is the faulting instruction (restart). Trap: saved PC is the next instruction.

Traps and GATE patterns

Connections

Builds on

I/O interface and programmed I/O

Unlocks

Instruction cycleuses Procedure calls and stack frames in hardwareanalogous to I/O interface and programmed I/Ocontrasts with Direct memory accesscontrasts with Structural, data and control hazardsuses System calls and kernel modePrerequisite of System calls and kernel modeimplemented by Critical section and race conditionsuses Test-and-set, swap and atomic instructionsuses I/O subsystem, buffering and spoolinguses

Across subjects

No cross-subject links yet.

Within this subject

I/O interface and programmed I/Ouses Instruction cycleimplemented-by Procedure calls and stack frames in hardwareanalogous-to Direct memory accesscontrasts-with Structural, data and control hazardsuses

An interrupt is an extra step of the instruction cycle, and saving the return address on the stack is the same mechanism as a call in stack frames. It is the middle scheme between polling and DMA. In a pipeline an interrupt must leave the machine in a state as if the instructions before the interrupted one had completed and none after had started (a precise interrupt), which is part of the difficulty of pipeline hazards.

PYQs

12 previous year questions from your book. I re-solved each one myself (4 by running or simulating, 8 by reasoning only); the book's key is shown next to my answer. All PYQs

GATE 2018 · NAT · 1 markQ13 · page 476 of the book

The following are some events that occur after a
device controller issues an interrupt while the
process L is under execution.
(P) The processor pushes the process status of L
onto the control stack.
(Q) The processor finishes the execution of the
current instruction.
(R) The processor executes the interrupt service
routine.
(S) The processor pops the process status of L
from the control stack.
(T) The processor loads the new PC value based
on the interrupt.
Which one of the following is the correct order
in which these events above occur?

(a)QPTRS
(b)PTRSQ
(c)TRPQS
(d)QTPRS Computer Organization and Architecture GATE CSE – NAT 2016 SET- 2 (1-MARKS)

year not read yetQ23 · page 478 of the book

Which of the following must be true for the
RFE (Return From Exception) instruction on a
general purpose processor?
I.It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur
during execution of an RFE instruction

(a)I only
(b)II only
(c)I and II only
(d)I, II and III only

GATE 2007 · MCQQ27 · page 480 of the book

Consider the following program segment. Here
R1, R2 and R3 are the general purpose registers.

Instruction
Operation
Instruction
Size
(no. of
words)

MOV
R1,(3000)
R1←M[3000]
2
LOOP:
MOV
R2,(R3)
R2 ← [R3]
1

ADD
R2,R1
R2 ← R1+R2
1

MOV
(R3),R2
M[R3] ←R2
1

INC R3
R3 ← R3+1
1

DEC R1
R1 ← R1-1
1

BNZ
LOOP
Branch on not
zero
2

HALT
Stop
1

Assume that the content of memory location 3000
is 10 and the content of the register R3 is 2000 . The
content of each of the memory locations from 2000
to 2010 is 100 . The program is loaded from the
memory location 1000. All the numbers are in
decimal.
Assume that the memory is byte addressable and
the word size is 32 bits. If an interrupt occurs during
the execution of the instruction "INC R3", what
return address will be pushed on to the stack?

(a)1005
(b)1020
(c)1024
(d)1040

GATE 2013 · MCQ · 2 marksQ4 · page 490 of the book

Consider the following sequence of micro
-
operations.
MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation
performed by this sequence?
Computer Organization and Architecture

(a)Instruction fetch
(b)Operand fetch
(c)Conditional fetch
(d)Initiation of interrupt service

GATE 2026 · MCQQ1 · page 522 of the book

Consider the following two statements about
interrupt handling mechanisms in a CPU,
S1: In non-vectored interrupt mechanism, it
usually takes more time to start the Interrupt
Service Routine (ISR) when compared to that in a
vectored interrupt mechanism.
S2: In daisy-chain interrupt mechanism, the CPU
polls all the input devices individually to
determine the source of the interrupt.
Which one of the following options is correct with
respect to SI and S2?

(a)Both S1 and S2 are true
(b)Both S1 and S2 are false
(c)S1 is true and S2 is false
(d)S1 is false and S2 is true .

GATE 2025 · MCQQ2 · page 522 of the book

Suppose a program is running on a non-pipelined
single processor computer system. The computer
is connected to an external device that can
interrupt the processor asynchronously. The
processor needs to execute the interrupt service
routine (ISR) to serve this interrupt. The following
steps (not necessarily in order) are taken by the
processor when the interrupt arrives:
(i) The processor saves the content of the program
counter.
(ii) The program counter is loaded with the start
address of the ISR.
(iii) The processor finishes the present instruction.
Which ONE of the following is the CORRECT
sequence of steps?

(a)(iii), (i), (ii)
(b)(i), (iii), (ii)
(c)(i), (ii), (iii)
(d)(iii), (ii), (i)

GATE 2024 · MCQQ4 · page 522 of the book

Which one of the following statements is FALSE?

(a)In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
(b)For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
(c)Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
(d)The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

GATE 2023 · NAT · 1 markQ5 · page 522 of the book

A keyboard connected to a computer is used at a rate
of 1 keystroke per second The computer system
polls the keyboard every 10 ms to check for a
keystroke and consumes 100 μs (micro seconds) for
each poll. If it is determined after polling that a key
has been pressed, the system consumes an additional
Computer Organization and Architecture

200 μs to process the keystroke. Let T1 denote the
fraction of a second spent in polling and
processing a keystroke.
In an alternative implementation, the system uses
interrupts instead of polling. An interrupt is raised
for every keystroke. It takes a total of 1 ms for
servicing an interrupt and processing a keystroke.
Let T2 denote the fraction of a second spent in
servicing the interrupt and processing a keystroke.
The ratio T1 / T2 is
. (Rounded off to
one decimal place)

GATE 2020 · MCQ · 1 markQ8 · page 523 of the book

Consider the following statements.
I. Daisy chaining is used to assign priorities in
attending interrupts.
II. When a device raises a vectored interrupt, the
CPU does polling to identify the source of the
interrupt.
III. In polling, the CPU periodically checks the
status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA
controller can be bus masters at the same time.
Which of the above statements is/are TRUE?

(a)I and IV only
(b)I and II only
(c)III only
(d)I and III only

GATE 2011 · MCQQ14 · page 524 of the book

On a non-pipelined sequential processor, a
program segment, which is the part of the interrupt
service routine, is given to transfer 500 bytes from
an I/O device to memory.
Intialize the address register
Intilatize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address
register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is
equivalent to a machine instruction which takes one
clock cycle to execute if it is a non-load/store
instruction. The load-store instructions take two
clock cycles to execute.
The designer of the system also has an alternate
approach of using the DMA controller to implement
the same transfer. The DMA controller requires 20
clock cycles for initialization and other overheads.
Each DMA transfer cycle takes two clock cycles to
transfer one byte of data from the device to the
memory.
What is the approximate speed up when the DMA
controller based design is used in a place of the
interrupt driven program based input-output?

(a)3.4
(b)4.4
(c)5.1
(d)6.7

GATE 2009 · MCQQ15 · page 524 of the book

A CPU generally handles an interrupt by executing
an interrupt service routine

(a)as soon as an interrupt is raised
(b)by checking the interrupt register at the end of fetch cycle
(c)by checking the interrupt register after finishing the execution of the current instruction
(d)by checking the interrupt register at fixed time intervals

GATE 2005 · MCQ · 2 marksQ16 · page 524 of the book

A device with data transfer rate 10 KB/sec is
connected to a CPU. Data is transferred byte-wise.
Let the interrupt overhead be 4 μ sec The byte
transfer time between the device interface register
and CPU or memory is negligible.
What is the minimum performance gain of operating
the device under interrupt mode over operating it
under program controlled mode?
Computer Organization and Architecture

(a)15
(b)25
(c)35
(d)45

Self-check

Question 1

A device delivers 8-byte words at 2 MB/s and an interrupt costs 250 cycles in total. The CPU is 1 GHz. What fraction of the CPU does the device use?

Show answer

Events per second $= 2\,000\,000/8 = 250\,000$ . $250\,000 \times 250 / 10^9 = 0.0625$ , that is 6.25%.

Question 2

Vector $0\text{x}40$ , entries of 8 bytes, table base $2000_{16}$ : where is the entry?

Show answer

$2000_{16} + 64 \times 8 = 2000_{16} + 200_{16} = 2200_{16}$ .

Question 3

Two devices request at once: one is on a daisy chain nearer the CPU, the other farther. Which is served first, and what if the nearer one requests again just after being served?

Show answer

The nearer device. If it keeps requesting, the far one can wait indefinitely (starvation).

Question 4

Which of these cannot be masked: a timer interrupt, NMI, an overflow trap?

Show answer

NMI and the overflow trap. (The timer interrupt is an ordinary maskable external interrupt.)

Revision card

One-screen revision

Sampled at the end of an instruction; save PC and flags, disable, vector, ISR, return.
Vector entry $=$ base $+$ vector $\times$ size. The entry holds the ISR address.
Daisy chain: nearest wins. Parallel: encoder and mask.
Nested only if the new request has a higher priority; the stack unwinds in reverse.
Fault: restart the same instruction. Trap: continue at the next one.
Cost: rate $\times$ cycles per interrupt $/$ clock.

References

·Hamacher, Vranesic, Zaky, Computer Organization, 5th ed., Chapter 4 Input/Output Organization (interrupts, interrupt hardware, enabling and disabling, handling multiple devices, nested interrupts, exceptions)
·Morris Mano, Computer System Architecture, 3rd ed., Chapter 11 Input-Output Organization (priority interrupt, daisy chain, parallel priority, interrupt cycle)
·Silberschatz, Galvin, Gagne, Operating System Concepts, Chapter 1 and the I/O chapter (interrupts, interrupt vector, trap)

Verification

The interrupt cost arithmetic, the vector address, the daisy-chain grant rule (all request patterns up to 5 devices) and the nested-interrupt timeline are produced by the C programs on this page (npm run verify:c); scripts/enum-checks/coa_io.py checks the grant rule against a priority encoder and the nesting timeline against an independent per-tick priority scheduler on 3000 random scenarios. The interrupt animation is a machine run (scripts/gen-coa-io-traces.py) re-checked by tests/coa-io-traces.test.ts (SP, flag and R0 restored, accepted only at an instruction boundary, vector entry used). Naming varies between textbooks: some call every unplanned transfer an interrupt, some use trap for internal events and interrupt for external ones; the page follows the common GATE convention and says so where it matters. Details of real processors (which flags are pushed, whether interrupts are disabled automatically) differ and are shown as one idealised model. Textbook chapter titles are from memory. SECOND PASS (2026-11-02, done by the assistant, not a human check): every Self-check question was solved before the printed answer was read and all agreed; the definitions, worked examples, cheat box and traps were read claim by claim and the numbers re-derived by hand (long C programs were not re-read line by line: they are compiled and compared by npm run verify:c, and their printed outputs were checked against the prose). One inexact ratio fixed (polling costs more than three times, 20% against 6%, not exactly three times). Status raised to self-checked; verified needs a textbook or human check.

last verified: never

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I/O interface and programmed I/O

Direct memory access