I/O interface and programmed I/O

Why it exists

Devices are slow, many and different: a keyboard produces a few bytes a second, a disk millions. A processor cannot be wired to each of them directly, and it cannot wait for them. An I/O interface is the small circuit between the buses and a device. It gives the processor a uniform view (a few registers with addresses), hides the device's speed and format, and tells the processor when a transfer can happen. This page covers the registers and how they are addressed, how a single word crosses the interface, and the simplest way to run a transfer: the processor itself tests the device in a loop (programmed I/O). The better schemes, interrupts and DMA, are defined against it, and GATE asks you to compare the three by the fraction of CPU time they consume.

Prerequisites

None. This is a starting point.

No other concept page is needed, but the picture of fetching and executing instructions from the instruction cycle helps: programmed I/O is just a loop of ordinary instructions.

Precise definitions

Interface registers. A typical device interface offers, at fixed addresses:

• a data register (data in, data out, or both),
• a status register with bits such as READY (a word is available, or the device can accept one), BUSY and ERROR,
• a control register that the processor writes to start an operation, choose a mode or enable interrupts.

Reading the data register normally also tells the device that the word has been taken, which clears READY. This is how the interface knows the transfer is complete.

Addressing the registers.

• Memory-mapped I/O. The registers occupy addresses of the ordinary memory address space. Ordinary load, store, test and logic instructions (with all their addressing modes) operate on them, and no special instructions or control line are needed. The price: those addresses can no longer be used for memory, and the registers must never be cached or the processor would read an old status (memory interfacing shows the decoder that produces the device select).
• Isolated (port-mapped, I/O-mapped) I/O. There is a separate I/O address space reached by special instructions (IN and OUT) and a control signal that says "this address is an I/O port, not memory". All memory addresses remain available; the port numbers are usually few (an 8-bit port number gives 256 ports), and the processor needs the extra instructions and signal.

Ways to run a transfer.

• Programmed I/O (polling, busy waiting). The processor repeatedly reads the status register until READY is 1, then moves the word itself. The processor does nothing else while it waits.
• Interrupt-driven I/O. The processor works on something else; the device raises an interrupt request when it is ready and the processor runs a service routine that moves the word (interrupts).
• Direct memory access (DMA). A DMA controller moves a whole block between the device and memory by itself, and interrupts the processor once at the end (DMA).
• I/O processor (channel). A separate small processor with its own instructions runs I/O programs, taking the whole job off the CPU; DMA is its simplest form.

Data transfer across the interface.

• Synchronous: source and destination share a clock, and a word is transferred at a clock edge. Simple, but both sides must be able to keep up with the clock.
• Asynchronous: no common clock, so control lines say when data is valid. With a strobe, one control line from the source (or from the destination) marks the moment the data is valid; the source cannot tell whether the destination really took it. With handshaking, two lines pass signals in both directions. In the four-phase source-initiated handshake: (1) the source puts data on the bus and raises data valid; (2) the destination takes the data and raises data accepted; (3) the source drops data valid; (4) the destination drops data accepted. Each side waits for the other, so the transfer works whatever the two speeds are.
• Parallel transfer sends all the bits of a word at once on separate wires; serial transfer sends them one after another on one wire.
• Asynchronous serial transfer (as in a UART) sends each character in a frame: an idle line is 1; a start bit 0 begins the frame; then the data bits (least significant first), an optional parity bit, and one or two stop bits of value 1. For a frame of $f$ bits at $B$ bits per second the character rate is $B/f$ and the fraction of the line carrying data is $d/f$ for $d$ data bits. (For simple two-level signalling the baud rate equals the bit rate; that is the assumption throughout this page.)

Cost of polling. If a device must be serviced $r$ times per second (once per unit of data it delivers), the processor must poll at least $r$ times per second. If one poll costs $c$ cycles and the clock rate is $f_{clk}$,

$\text{fraction of CPU time spent polling} = \frac{r \cdot c}{f_{clk}}.$

Polling costs this whether or not the device has anything to send (the figure assumes the device is serviced exactly at its rate). Interrupt-driven I/O costs time only when an event happens, but each event is more expensive.

How it works

The first animation runs a polling loop on a small machine whose device registers are memory-mapped (STATUS at address F0, DATA at F1). Watch the wasted passes: the CPU reads STATUS again and again while the device is not ready, and it moves each of the three words itself.

The second animation shows the four-phase handshake that makes an asynchronous transfer safe. Notice that the data is on the bus before valid rises and stays there until accepted has been seen.

The third animation puts the same job, three words arriving at ticks 6, 16 and 26, through the three schemes on one time axis. Count the ticks marked work: polling gets 8 of 36, interrupt-driven I/O 27, DMA 29. The numbers are a model (the costs per word are the ones stated in the steps), but the ordering and the reason for it are general.

Worked examples

#include <stdio.h>
 
static void row(const char *name, double bytes_per_s, double unit_bytes, double cycles, double clock) {
    double polls = bytes_per_s / unit_bytes;
    printf("%-7s %8.0f polls/s -> %8.4f%% of the CPU\n", name, polls, 100.0 * polls * cycles / clock);
}
 
int main(void) {
    /* every poll costs 400 cycles; the CPU runs at 500 MHz */
    row("mouse", 30, 1, 400, 500e6);
    row("floppy", 50e3, 2, 400, 500e6);
    row("disk", 4e6, 16, 400, 500e6);
    return 0;
}

mouse         30 polls/s ->   0.0024% of the CPU
floppy     25000 polls/s ->   2.0000% of the CPU
disk      250000 polls/s ->  20.0000% of the CPU

#include <stdio.h>
 
/* a device whose ready bit shows up on the 4th read of its status register */
static int status_reads;
static unsigned read_status(void) { return ++status_reads >= 4; }
static unsigned read_data(void) { return 0x41; }
 
int main(void) {
    int wasted = 0;
    while (!read_status()) wasted++;      /* busy waiting: the polling loop */
    unsigned word = read_data();
    printf("status read %d times, %d passes wasted, data = 0x%02X\n", status_reads, wasted, word);
    return 0;
}

status read 4 times, 3 passes wasted, data = 0x41

#include <stdio.h>
 
static void line(const char *name, int baud, int start, int data, int parity, int stop) {
    int frame = start + data + parity + stop;
    printf("%-4s frame of %2d bits: %6.1f characters/s, %5.1f%% of the bits are data\n", name, frame, (double)baud / frame, 100.0 * data / frame);
}
 
int main(void) {
    line("8N1", 9600, 1, 8, 0, 1);
    line("8E2", 9600, 1, 8, 1, 2);
    line("7E1", 9600, 1, 7, 1, 1);
    return 0;
}

8N1  frame of 10 bits:  960.0 characters/s,  80.0% of the bits are data
8E2  frame of 12 bits:  800.0 characters/s,  66.7% of the bits are data
7E1  frame of 10 bits:  960.0 characters/s,  70.0% of the bits are data

Cheat box

Traps and GATE patterns

Connections

Device registers placed in the address space are the memory-mapped case of memory interfacing. The instruction that polls is an ordinary instruction of the instruction cycle. The two alternatives to polling are interrupts, which let the device announce itself, and DMA, which takes the CPU out of the data path altogether.

PYQs

Which one of the following statements is FALSE?

A keyboard connected to a computer is used at a rate
of 1 keystroke per second The computer system
polls the keyboard every 10 ms to check for a
keystroke and consumes 100 μs (micro seconds) for
each poll. If it is determined after polling that a key
has been pressed, the system consumes an additional
Computer Organization and Architecture

200 μs to process the keystroke. Let T1 denote the
fraction of a second spent in polling and
processing a keystroke.
In an alternative implementation, the system uses
interrupts instead of polling. An interrupt is raised
for every keystroke. It takes a total of 1 ms for
servicing an interrupt and processing a keystroke.
Let T2 denote the fraction of a second spent in
servicing the interrupt and processing a keystroke.
The ratio T1 / T2 is
. (Rounded off to
one decimal place)

A device with data transfer rate 10 KB/sec is
connected to a CPU. Data is transferred byte-wise.
Let the interrupt overhead be 4 μ sec The byte
transfer time between the device interface register
and CPU or memory is negligible.
What is the minimum performance gain of operating
the device under interrupt mode over operating it
under program controlled mode?
Computer Organization and Architecture

Normally user programs are prevented from
handling I/O directly by I/O instructions in them.
For CPUs having explicit I/O instructions, such I/O
protection is ensured by having the I/O instruction
privileged. In a CPU with memory mapped I/O,
there is no explicit I/O instruction. Which one of the
following is true for a CPU with memory mapped
I/O?

Self-check

Revision card

References